The present invention relates generally to integrated circuits, and, more particularly, to a charge pump circuit.
Integrated circuits include analog and digital circuits such as phase-locked loops (PLLs), delay-locked loops (DLLs), analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and memories, which require different supply voltages for performing various operations. Integrated circuits that receive a single power supply voltage often include a charge pump. The charge pump is a voltage converter that includes capacitors to store and transfer energy. The charge pump receives an input supply voltage and generates an output voltage that is different from the input supply voltage.
Traditionally, a charge pump includes at least two capacitors, which are generally very big to counter leakage and parasitics, that constitute most of the charge pump. Given a particular capacitor size, charge pump leakage determines the frequency at which it should be refreshed. The higher the leakage, the faster the charge pump output drops and needs to be refreshed. Further, as the circuit charge pumps the voltage, it generally must use higher rated devices than the devices already being used in the charge pump design. The traditional single capacitor charge pump has low output voltage control, which restricts the circuit to being operated in a certain common mode voltage range. This becomes a big restriction when trying to optimize the charge pump for lowest power and highest speed/resolution.
Referring to FIG. 1, a schematic circuit diagram of a conventional charge pump 100 is shown. The charge pump 100 includes a first complementary metal-oxide semiconductor (CMOS) inverter 102, a capacitor 104, a diode 106, and a second CMOS inverter 108.
The diode 106 has a first terminal connected to a voltage source (not shown) for receiving a supply voltage VDD, and a second terminal connected to the CMOS inverter 102 and a first terminal of the capacitor 104. The capacitor 104 receives an input clock signal VINPUT_CLK its second terminal.
The first CMOS inverter 102 includes a p-channel metal-oxide semiconductor (PMOS) transistor 110 and an n-channel metal-oxide semiconductor (NMOS) transistor 112. The PMOS transistor 110 has a gate terminal for receiving an inverted version of the input clock signal VINV_CLK (hereinafter the “inverted input clock signal VINV_CLK”), and a source terminal connected to the second terminal of the diode 106. The NMOS transistor 112 has a gate terminal for receiving the inverted input clock signal VINV_CLK and a source terminal connected to ground. The NMOS transistor 112 has a drain terminal connected to a drain terminal of the PMOS transistor 110 for generating an output voltage VOUT.
The second CMOS inverter 108 receives the input clock signal VINPUT_CLK and generates and provides the inverted input clock signal VINV_CLK to the first CMOS inverter 102.
Initially, the input clock signal VINPUT_CLK is low (i.e., logic low state), so the inverted input clock signal VINV_CLK is high. The NMOS transistor 112 receives the inverted input clock signal VINV_CLK at its gate terminal and hence, is turned ON, thereby providing the output voltage VOUT at a logic low state. Meanwhile, the capacitor 104 is charged to a first voltage level by current flowing through the diode 106. The first voltage level is approximately equal to the supply voltage VDD.
When the input clock signal VINPUT_CLK transitions from low to high, the first terminal of the capacitor 104 is raised to a second voltage level—the second voltage level is a sum of the first voltage level and a voltage level of the input clock signal VINPUT_CLK. The voltage level of the input clock signal VINPUT_CLK when the input clock signal VINPUT_CLK is high is approximately equal to VDD. Thus, the second voltage level is approximately equal to 2*VDD. Hence, the second terminal of the diode 106 is at a higher voltage level than its first terminal, so the diode 106 is reverse biased. The NMOS transistor 112 receives the low inverted input clock signal VINV_CLK at its gate so the NMOS transistor 112 is switched OFF. The source terminal of the PMOS transistor 110 is connected to the first terminal of the capacitor 104. Hence, the source terminal of the PMOS transistor 110 is at the second voltage level. As the gate terminal of the PMOS transistor 110 receives the inverted input clock signal VINV_CLK at logic low state, the PMOS transistor 110 is switched ON, thereby providing the output voltage VOUT at the second voltage level. Thus, when the input clock signal VINPUT_CLK is at low, the voltage level of the output voltage VOUT is approximately equal to zero and when the input clock signal VINPUT_CLK is high, the voltage level of the output voltage VOUT is approximately equal to 2*VDD.
However, the charge pump 100 does not provide control over the voltage level of the output voltage VOUT, i.e, the charge pump 100 does not provide the output voltage VOUT at a voltage level that is substantially greater than VDD and substantially less than 2*VDD. Thus, the charge pump 100 fails to provide the output voltage VOUT at a voltage level of 1.5*VDD. During charge pump operation, power dissipation in the charge pump 100 due to charge leakage through the diode 106 and the NMOS transistor 112 is high, which results in a high refresh rate of the capacitor 104. Further, the above technique cannot be modified to provide the output voltage VOUT at a voltage level less than ground, i.e., the charge pump 100 cannot be modified to operate as a negative charge pump.
It would be advantageous to have a charge pump that provides a controlled output voltage and has reduced power consumption.